Additional Technical References
Chapter 10: Layout Parasitic Extraction and Electrical Modeling
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Nabors, Keith, and White, Jacob, "Fast Capacitance Extraction of General Three-Dimensional Structures", IEEE Transactions on Microwave Theory and Techniques, Volume 40, Number 7, July 1992, p. 1496 - 1506.
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Loh, W.M., et al, "Modeling and Measurement of Contact Resistances", IEEE Transactions on Electron Devices, Vol. ED-34, No. 3, March, 1987, p. 512-524.
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Murrmann, H., and Widmann, D., "Current Crowding on Metal Contacts to Planar Devices", IEEE Transactions on Electron Devices, Vol. ED-16, No. 12, December 1969, p. 1022-1024.
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Restle, P., et al., "Measurement and Modeling of On-Chip Transmission Line Effects in a 400MHz Microprocessor", IEEE Journal of Solid-State Circuits, Vol. 33, No. 4, April 1998.
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Deutsch, A., et al., "When are Transmission-Line Effects Important for On-Chip Interconnections?", IEEE Trans. on Microwave Theory and Techniques, Vol. 45, No. 10, October, 1997.
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Yu, W. and Wang, X., Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits, Springer, 2014. (Chapter 2: Basic Field-Solver Techniques for RC Extraction)
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Wu, Wen and Chan, Mansun, "Gate Resistance Modeling of Multifin MOS Devices", IEEE Electron Device Letters, Volume 27, Number 1, January 2006, p. 68-70.
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Khandelwal, S., et al, "New Industry Standard FinFET Model for Future Technology Nodes", Proceedings of the 2015 Symposium on VLSI Technology, p. T62-T63 (paper 6-4)
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Liao, H., et al., "Integration of CMP Modeling in RC Extraction and Timing Flow", Custom Integrated Circuits Conference, 2007.
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El-Modelhy, T., et al, "A Hierarchical Floating Random Walk Algorithm for Fabric-Aware 3D Capacitance Extraction", Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), 2009, p. 752-758.
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Kao, W., et al., "Parasitic Extraction: Current State of the Art and Future Trends", Proceedings of the IEEE, Vol. 89, No. 5, May 2001.
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Arora, N., et al., "Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits", IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 15, No. 1, January, 1996.
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Hatami, S., et al., "Efficient Compression and Handling of Current Source Model Library Waveforms", Conference on Design, Automation, and Test in Europe (DATE), April 2009, p. 1178-1183.
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Restle, Phillip, et al., "Multi-GHz Interconnect Effects in Microprocessors", IEEE International Symposium on Physical Design (ISPD), 2001, p. 93-97.
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Byron Krauter and Sharad Mehrotra, "Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis", IEEE Design Automation Conference (DAC), 1998, p. 303-308.
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Ismail, Y., et al., "Figures of Merit to Characterize the Importance of On-Chip Inductance", IEEE Design Automation Conference (DAC), 1998, p. 560-565.
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Sun S., et al., "Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 7, July 2015, p. 1096-1109.
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Ho, Ron, et al., "The Future of Wires", IEEE Proceedings, Vol. 89, Issue 4, 2001.
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Chen, Xiaoming, et al., "Parallel Circuit Simulation on Multi/Many-core Systems", IEEE International Parallel and Distributed Processing Symposium, 2012, p. 2530-2533.