© 2019 by Thomas Dillinger

Additional Technical References

Chapter 10:   Layout Parasitic Extraction and Electrical Modeling

  1. Nabors, Keith, and White, Jacob, "Fast Capacitance Extraction of General Three-Dimensional Structures", IEEE Transactions on Microwave Theory and Techniques, Volume 40, Number 7, July 1992, p. 1496 - 1506.

  2. Ratzlaff, Curtis, and Pillage, Lawrence, "RICE: Rapid Interconnect Circuit Evaluation Using AWE", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 13, Number 6, June 1994, p. 763 - 776.

  3. Loh, W.M., et al, "Modeling and Measurement of Contact Resistances", IEEE Transactions on Electron Devices, Vol. ED-34, No. 3, March, 1987, p. 512-524.

  4. Murrmann, H., and Widmann, D., "Current Crowding on Metal Contacts to Planar Devices", IEEE Transactions on Electron Devices, Vol. ED-16, No. 12, December 1969, p. 1022-1024.

  5. Yu, W. and Wang, X., Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits, Springer, 2014.  (Chapter 2:  Basic Field-Solver Techniques for RC Extraction)

  6. Wu, Wen and Chan, Mansun, "Gate Resistance Modeling of Multifin MOS Devices", IEEE Electron Device Letters, Volume 27, Number 1, January 2006, p. 68-70.

  7. Khandelwal, S., et al, "New Industry Standard FinFET Model for Future Technology Nodes", Proceedings of the 2015 Symposium on VLSI Technology, p. T62-T63 (paper 6-4)

  8. El-Modelhy, T., et al, "A Hierarchical Floating Random Walk Algorithm for Fabric-Aware 3D Capacitance Extraction", Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), 2009, p. 752-758.