Additional Technical References

Chapter 5:   Characteristics of Functional Validation

  1. Spear, Chris, SystemVerilog for Verification, Springer, ISBN 0-387-27036-1, 2006.

  2. Krishnaswamy, V., "Implications of VHDL Timing Models on Simulation and Software Synthesis", Journal of Systems Architecture: the EUROMICRO Journal, October, 1997, p. 23-36. 

  3. Chen, Xiaoming, et al., "Parallel Circuit Simulation on Multi/Many-core Systems", 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, p. 2530 - 2533.

  4. Majewski, M.L., "A nonlinear macromodel of operational amplifiers in the frequency domain", IEEE Transactions on Circuirs, Volume CAS-26, June, 1979, p. 395 - 402.

  5. Beece, D., et al, "The IBM Engineering Verification Engine", Proceedings of the 25th IEEE Design Automation Conference (DAC), 1988, p. 218-224 (paper 17.1).

© 2019 by Thomas Dillinger