© 2019 by Thomas Dillinger

Additional Technical References

EPILOGUE

  1. Murdoch, Gayle, et al., "Feasibility Study of Fully Self Aligned Vias for 5nm Node BEOL", IEEE International Interconnect Technology Conference (IITC), 2017, p. 2380 - 2382.

  2. Bae, Geumjong, et al., "3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications", IEEE International Electron Devices Meeting (IEDM), 2018, p. 28.5.1 - 28.7.4.

  3. Lanzillo, N., et al., "Impact of Line and Via Resistance on Device Performance for 5nm Gate All Around Node and Beyond", 2018, IEEE International Interconnect Technology Conference (IITC), p. 70-72.