Additional Technical References


  1. Murdoch, Gayle, et al., "Feasibility Study of Fully Self Aligned Vias for 5nm Node BEOL", IEEE International Interconnect Technology Conference (IITC), 2017, p. 2380 - 2382.

  2. Bae, Geumjong, et al., "3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications", IEEE International Electron Devices Meeting (IEDM), 2018, p. 28.5.1 - 28.7.4.

  3. Lanzillo, N., et al., "Impact of Line and Via Resistance on Device Performance for 5nm Gate All Around Node and Beyond", 2018, IEEE International Interconnect Technology Conference (IITC), p. 70-72.

  4. Hu, Y.H., et al., "Cu-Cu Hybrid Bonding as Option for 3D IC Stacking", 2012 IEEE International Interconnect Technology Conference.

  5. Vaidyanathan, K., et al., "Building Trusted ICs using Split Fabrication", IEEE Int'l. Symposium on Hardware-Oriented Security and Trust (HOST), 2014, p. 1-6. 

© 2019 by Thomas Dillinger