Chapter 1:    Introduction

Chapter 2:    VLSI Design Methodology

Chapter 3:    Hierarchical Design Decomposition

Chapter 4:    Cell and IP Modeling

Chapter 5:    Characteristics of Functional Validation

Chapter 6:    Characteristics of Formal Verification

Chapter 7:    Logic Synthesis

Chapter 8:    Placement

Chapter 9:    Routing

Chapter 10:  Layout Parasitic Extraction and Electrical Modeling

Chapter 11:  Timing Analysis

Chapter 12:  Noise Analysis

Chapter 13:  Power Analysis

Chapter 14:  Power Rail Voltage Drop Analysis

Chapter 15:  Electromigration (EM) Reliability Analysis

Chapter 16:  Miscellaneous Electrical Analysis Requirements

Chapter 17:  ECOs

Chapter 18:  Physical Design Verification

Chapter 19:  Design-for-Testability Analysis

Chapter 20:  Preparation for Tapeout

Chapter 21:  Post-silicon Design and Characterization

EPILOGUE

​

​