Additional Technical References

Chapter 11:   Timing Analysis 

  1. Peter O'Brien and Thomas Savarino, "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation", IEEE Int'l. Conference on Computer-Aided Design (ICCAD), 1989, p. 512-515.

  2. Alpert, Charles, et al., "Closed-Form Delay and Slew Metrics Made Easy", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 23, Number 12, December 2004, p. 1661 - 1669.

  3. Dasdan, Ali, et al., "Derating for Static Timing Analysis: Theory and Practice", 10th IEEE International Symposium on Quality Electronic Design, 2009, p. 719 - 727.

  4. Alpert, Charles, et al., "Delay and Slew Metrics Using the Lognormal Distribution", IEEE Design Automation Conference, 2003, p. 382 - 385.

  5. Tehrani, P.F., et al., "Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk", IEEE International Symposium on Quality Electronic Design, 2000, p. 505 - 512.

  6. Qin., Z., and Cheng, C.K., "Basics of Circuit Analysis" (Chapter 2), Symbolic Analysis and Reduction of VLSI Circuits, Springer, ISBN: 978-0-387-23904-0, 2005.

  7. Macys, R., and McCormick, S., "A New Algorithm for Computing the Effective Capacitance in Deep Sub-micron Circuits", IEEE Custom Integrated Circuits Conference (CICC), 1998, p. 313-316.

  8. Abbaspour, S., and Pedram, M., "Calculating the Effective Capacitance for the RC Interconnect in VDSM Technologies", Proceedings of the 2003 Asia and South Pacific Design Automation Conference (ASP-DAC).

  9. Daga, Ajay, et al., "Automated Timing Model Generation", Design Automation Conference (DAC), June 2002. 

  10. Gupta, R., et al., "The Elmore Delay as a Bound for RC Trees with Generalized Input Signals", Proceedings of the 32nd IEEE Design Automation Conference (DAC), 1995.

  11. Qian, Jessica, et al., "Modeling the Effective Capacitance for the RC Interconnect of CMOS Gates", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 12, December 1994, p. 1526-1535.

  12. Zhou, Dian, et al., "Interconnection Delay in Very High-Speed VLSI", IEEE Trans. on Circuits and Systems, Vol. 38, No. 7, July 1991, p. 779-790.

  13. Chen, Kai, et al., "Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects", IEEE Transactions on Electron Devices, Vol. 44, No. 11, Nov. 1997, p. 1951-1957.

  14. David Du, et al., "On the General False Path Problem in Timing Analysis", IEEE Design Automation Conference (DAC), 1989, p. 555-560.

  15. Hitchcock, R., et al., "Timing Analysis of Computer Hardware", IBM J. of Research & Development, Vol. 26, No 1., January 1982, p. 100-105.

  16. Ratzlaff, C., et al., "Modeling the RC-Interconnect Effects in a Hierarchical Timing Analyzer", IEEE Custom Integrated Circuits Conference (CICC), 1992, p. 15.6.1-4.

  17. Gopal, N., et al., "Evaluating RC-Interconnect Using Moment-Matching Approximations", IEEE Int'l. Conference on Computer-Aided Design (ICCAD), 1991, p. 74-77. 

  18. Yang, P., et al., "An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design", IEEE Trans. on Computer-Aided Design, Vol. CAD-5, No. 1, January 1986, p. 5-14.

  19. Puri, Yogishwar, "On the Logic Delay in MOS LSI Static NOR Designs", IEEE J. of Solid-State Circuits, Vol. SC-14, No. 4, 1979, p. 716-723.

  20. Saraswat, Krishna, et al., "Effect of Scaling on Interconnections on the Time Delay of VLSI Circuits", IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April, 1982, p. 645-650. 

  21. Lovett, S., et al., "Optimizing MOS Transistor Mismatch", IEEE Journal of Solid-State Circuits, 1998, Vol. 33, Issue 1.

  22. Pelgrom, M., et al., "Matching Properties of MOS Transistors", IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989.  

  23. Keuhlmann, Andreas, and Bergamaschi, Reinaldo, "Timing Analysis in High-Level Synthesis", Proceedings of the International Conference on Computer-Aided Design (ICCAD), 1992, p. 349-354.

  24. Pillage, L., and Rohrer, R., "Asymptotic Waveform Evaluation for Timing Analysis", IEEE Transactions on Computer-Aided Design, Vol. 9, No. 4, April 1990, p. 352-366.

  25. Brashear, R., et al., "ETA:  Electrical-Level Timing Analysis", IEEE International Conference on Computer-Aided Design (ICCAD), 1992, p. 258-262.

  26. Tutuianu, B., et al., "An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response", IEEE Design Automation Conference (33rd DAC), 1996, p. 611-616.

© 2019 by Thomas Dillinger