© 2019 by Thomas Dillinger

Additional Technical References

Chapter 11:   Timing Analysis 

  1. Alpert, Charles, et al., "Closed-Form Delay and Slew Metrics Made Easy", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 23, Number 12, December 2004, p. 1661 - 1669.

  2. Dasdan, Ali, et al., "Derating for Static Timing Analysis: Theory and Practice", 10th IEEE International Symposium on Quality Electronic Design, 2009, p. 719 - 727.

  3. Alpert, Charles, et al., "Delay and Slew Metrics Using the Lognormal Distribution", IEEE Design Automation Conference, 2003, p. 382 - 385.

  4. Tehrani, P.F., et al., "Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk", IEEE International Symposium on Quality Electronic Design, 2000, p. 505 - 512.

  5. Qin., Z., and Cheng, C.K., "Basics of Circuit Analysis" (Chapter 2), Symbolic Analysis and Reduction of VLSI Circuits, Springer, ISBN: 978-0-387-23904-0, 2005.

  6. Macys, R., and McCormick, S., "A New Algorithm for Computing the Effective Capacitance in Deep Sub-micron Circuits", IEEE Custom Integrated Circuits Conference (CICC), 1998, p. 313-316.

  7. Abbaspour, S., and Pedram, M., "Calculating the Effective Capacitance for the RC Interconnect in VDSM Technologies", Proceedings of the 2003 Asia and South Pacific Design Automation Conference (ASP-DAC).

  8. Gupta, R., et al., "The Elmore Delay as a Bound for RC Trees with Generalized Input Signals", Proceedings of the 32nd IEEE Design Automation Conference (DAC), 1995.