Additional Technical References

Chapter 12:   Noise Analysis

  1. Cong, Jason, et al., "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization", Proceedings of the 2001 Asia and South Pacific Design Automation Conference (ASP-DAC'01), p. 373 - 378.

  2. Levy, Rafi, et al., "ClariNet: A noise analysis tool for deep submicron design", Design Automation Conference, 2000, p. 233 - 238.

  3. Tseng, K., and Kariat, V., "Static noise analysis with noise windows", Design Automation Conference, 2003, p. 864 - 868.

  4. Ding, Li, et al., "Efficient Crosstalk Noise Modeling Using Aggressor and Tree Reductions", Proceedings of the 2002 IEEE International Conference on Computer-Aided Design (ICCAD), p. 595 - 600.

  5. Chai, D., et al., "Temporofunctional crosstalk noise analysis", Design Automation Conference 2003, p. 860 - 863.

  6. Varshney, G.K., et al., "An Efficient Methodology for Noise Characterization", IEEE International Symposium on Quality Electronic Design, 2000, p. 330 - 336.

  7. Chandrasekar, S., et al., "A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries", Proceedings of the IEEE Sixth International Symposium on Quality Electronic Design (ISQED), 2005, p. 530-535.

  8. Papadopoulos, P., et al., "Challenges and Trends in SOC Electromagnetic (EM) Crosstalk", IEEE International Verification and Security Workshop (IVSW), 2017. 

  9. Raman, A., et al., "Electromagnetic (EM) Crosstalk Failures and Symptoms in SoC Designs", IEEE International Workshop on Microprocessor and SoC Test and Verification, 2017.

© 2019 by Thomas Dillinger