Additional Technical References

Chapter 19:   Design-for-Testability Analysis

  1. Zarrineh, K., et al., "Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors", IEEE International Conference on Computer Design (ICCD), 2001, p. 526 - 529.

  2. Lu, Binghua, et al., "The Test Cost Reduction Benefits of Combining a Hierarchical DFT Methodology with EDT Channel Sharing -- A Case Study", 2018 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

  3. Huang, Yu, et al., "Test Compression Improvement with EDT Channel Sharing in SoC Designs", 2014 IEEE 23rd North Atlantic Test Workshop, p. 22 - 31.

  4. Horiguchi, M., and Itoh, H., Nanoscale Memory Repair, Springer, 2011.

  5. Hapke, F., et al., "Cell-Aware Test", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 9, September 2014, p. 1396-1409.

  6. Tasi, Kun-Han and Sheng, Shuo, "Design Rule Check on Clock Gating Logic for Testability and Beyond", IEEE International Test Conference (ITC), 2013, Paper 15.2.

  7. Raina, Rajesh, "What is DFM & DFY and Why Should I Care?", IEEE International Test Conference (ITC), 2006, Lecture 3.1.

  8. Rizzolo, R.F., et al, "IBM System z9 eFUSE applications and methodology", IBM Journal of Research and Development, Volume 51, Number 1/2, January/March, 2007, p. 65-75.

© 2019 by Thomas Dillinger