Additional Technical References

Chapter 16:   Miscellaneous Electrical Analysis Requirements

  1. Yu, Fa-Xin, et al., "Overview of Radiation Hardening Techniques for IC Design", Information Technology Journal, Volume 9, Issue 6, 2010, p. 1068 - 1080.

  2. Hutson, John, et al., "The Effects of Scaling and Well and Substrate Contact Placement on Single Event Latchup in Bulk CMOS Technology", IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2005, PC24-1 - PC24-5.

  3. Malkov, A., et al., "A Review of PVT Compensation Circuits for Advanced CMOS Technologies", Circuits and Systems, Volume 2, Number 3, July 2011, p. 162 - 169.

  4. Dabral, Sanjay, and Maloney, Timothy J., Basic ESD and I/O Design, Wiley-Interscience, ISBN 0-471-25359-6, 1998.

  5. Dutertre, J.M., Roche, F.M., and Cathebras, G., "Integration of Robustness in the Design of a Cell", SoC Design Methodologies, Springer, Boston MA, p. 229-239.

  6. Zhang, et al., "Sequential Element Design with Built-In Soft Error Resilience", IEEE Transactions on VLSI Systems, Volume 14, Issue 12, December, 2006, p. 1368-1378.

  7. Joshi, V., et al., "Logic SER Reduction through Flipflop Redesign", Proceedings of the 7th International Symposiumm on Quality Electronic Design (ISQED), 2006.

  8. Wu, Chiang, and Marculescu, Diana, "Clock Skew Scheduling for Soft-Error-Tolerant Sequential Circuits", Proceedings of the 2010 Design, Automation, and Test in Europe Conference (DATE).

  9. Gao, X.F., et al, "Implementation of a Comprehensive MOSFET Model in Cadence SPICE for ESD Applications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 21, Number 12, December 2002, p. 1497-1502.

  10. Chandra, V., et al., "Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS", 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, Oct. 2008.

  11. Hutson, J., et al., "The Effects of Scaling and Well and Substrate Contact Placement on Single Event Latchup in Bulk CMOS Technology", IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2005, PC24, p. 1-5. 

  12. Wu, Kai-Chiang and Marculescu, Diana, "Clock Skew Scheduling for Soft-Error-Tolerant Sequential Circuits", Design, Automation and Test Conference in Europe (DATE) 2010, p. 717-722.

  13. Zhou, Quming, and Mohanram, Kartik, "Cost-Effective Radiation Hardening Technique for Combinational Logic", Int'l. Conf. on Computer-Aided Design (ICCAD), 2004.

  14. Holcomb, D., et al., "Design as you see FIT:  System-Level Soft Error Analysis of Sequential Circuits", Design Automation and Test Conference in Europe (DATE), 2009.

  15. Joshi, Vivek, et al., "Logic SER Reduction through Flipflop Redesign", ISQED 2006, p. 611-616.

  16. Faccio, F., et al., "SEU effects in registers in a Dual-Ported Static RAM design in a 0.25um CMOS technology", Proceedings of the Fifth Workshop on Electronics for LHC Experiments, September 1999, p. 571-575.

  17. Zhang, et al, "Sequential Element Design with Built-In Soft Error Resilience (BISER)", IEEE Trans. on VLSI Systems, Vol. 14, No. 12, Dec. 2006, 1368-1378.  

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