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Additional Technical References

Chapter 9:   Routing

  1. Dong, X., et al, "New Metal Fill Considerations for Nanometer Technologies", 6th International Conference on ASIC (ASICON), 2005, p. 804-807.

  2. Cong, Jason, et al., "Performance-Driven Interconnect Design Based on Distributed RC Delay Model", IEEE Design Automation Conference (DAC), 1993, p. 606-611.

  3. Cong, Jason, et al., "Optimal Wiresizing Under the Distributed Elmore Delay Model", IEEE Int'l. Conf. on Computer-Aided Design (ICCAD), 1993, p. 634-639. 

  4. Sachin Sapatnekar, "RC Interconnect Optimization under the Elmore Delay Model", IEEE Design Automation Conference (DAC), 1994, p. 387-391.

  5. Cong, Jason, et al., "Simultaneous Driver and Wire Sizing for Performance and Power Optimization", IEEE Trans. on VLSI Systems, Vol. 2, No. 4, 1994, p. 206-212.

  6. Clein, Dan, CMOS IC Layout: concepts, methodologies, and tools, Newnes Press, 1999. 

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